The present invention relates to a non-inverting buffer device and a semiconductor storage device, and more particularly to a non-inverting buffer circuit device and a semiconductor storage circuit device with a high operation speed.
A general dynamic type semiconductor memory (hereinafter referred to as DRAM) to which the present invention can be applied would typically include an input buffer circuit, a row decoder circuit, a column decoder circuit, a memory cell array, an amplifier circuit and an output buffer circuit. FIG. 8 is a block diagram of an example of such a DRAM. In FIG. 8, in accordance with an addressing signal Ai, an input buffer circuit 10 supplies a signal for addressing to both the row decoder circuit 11 and the column decoder circuit 12. An amplifier circuit 13 and an output buffer circuit 14 are also provided. A row address decoder circuit 11 and a column decoder circuit 12 supplies a row address and a column address to a memory cell array 15, respectively.
The memory cell array 15 is composed of memory cells arranged in a matrix shape of 2.sup.M .times.2.sup.N (M, N are positive integers). The amplifier circuit 13 amplifies the signal from the memory cell array 15 to send the amplified signal to the output buffer circuit 14. The output buffer circuit 14 sends an input signal from the memory cell array 15 to a succeeding stage circuit.
Generally, high speed operation has been demanded for semiconductor memories. The operation speed is defined by the time taken from when the address signal Ai is inputted to the input buffer circuit 10 to the time when the information stored in the memory cell selected by the address signal Ai is read out from the output buffer circuit 14 (now called `delay time`), i.e., an access time.
The access time can be shortened by enhancing the operation speed of each of the components of the semiconductor memory. Particularly, realizing the high speed operation of the input buffer circuit 10 is very effective because it contributes to the high speed operation of each of the succeeding stage circuits (the row decoder circuit 11, column decoder circuit 12 and memory cell array 12) as well as the high speed operation of itself.
The input buffer circuit for a DRAM, as described later with reference to FIGS. 2A and 2B, is required to have, as its characteristic functions, (1) a complementary signal outputting function, (2) an output latch function, (3) a set/reset function and (4) a refresh function.
(1) The complementary signal outputting function is to output two output signals AN and AP (hereinafter, as the case may be, both output signals AN and AP may be expressed as a complementary signal) indicative of different logic levels.
(2) The output latch function is to latch a complementary signal outputted in accordance with the address signal Ai to fix the output regardless of a change in the address signal Ai.
(3) The set/reset function is a switch over function to either send the complementary signals according to the address signal Ai to the respective succeeding stage decoder circuits 11 and 12 to output desired data at a memory cell (set mode) or, on the contrary, to send fixed signals both of which are at a `H` (or `L`) level regardless of the address signal Ai to the respective decoder circuits 11 and 12 so that selection of the memory cell by the decoder circuits is inhibited to place DRAM in a standby state (reset mode).
(4) The refresh function is to rewrite the storage contents of a memory cell (e.g. for 2-3 ms) to prevent the stored data from being destroyed.
FIG. 2A shows the circuit structure of the input buffer circuit 10 for the conventional DRAM in its block form, and FIG. 2B is the corresponding timing chart.
The input buffer circuit for DRAM is mainly composed of a level inverting circuit section, a complementary signal creating circuit section, an isolation circuit unit, a refresh address input circuit stage (section), a self-latch circuit stage (section) and a driver circuit stage (section).
The level inverting section is constructed by a two-input NAND gate IC1 for inverting, in response to input signals of an address signal and a control signal .phi., the logical level (e.g. 0-3 V) of the address signal Ai to that suitable for the DRAM (e.g. 0-5 V) so that if the control signal .phi. is at a logical low `L` level, the output signal is fixed at a logical high `H` level regardless of the value of the address signal Ai and if the control signal .phi. is at the `H` level, the inverted signal of the address signal Ai is outputted.
The complementary signal creating circuit is composed of an inverter IC2 and two NAND gates IC3a and IC3b. In the set mode, the control signal .phi. is at the `H` level so that the inverting signal of the address signal Ai is outputted from IC3a and the non-inverting is outputted from IC3b. In the reset mode, the control signal .phi. is at the `L` level so that both outputs from IC3a and IC3b are at the `H` level regardless of the value of the address signal Ai. Incidentally, the circuit structures after IC3a and IC3b are entirely the same on both sides of the inverting output and non-inverting output so that the explanation will be given of only the inverting output side.
The isolation circuit section is a clocked inverter IC4 composed of p-channel MOS transistors (hereinafter referred to as pMOS) Q1, Q3 and n-channel MOS transistor (hereinafter referred to as nMOS) Q2, Q4. If a control signal .phi.2 is at the `H` level (.phi.2 is at the `L` level), Q3 and Q4 turn on so that the separation circuit serves as an inverter, whereas if the control signal .phi.2 is at the `L` level, Q3 and Q4 turn off so that the separation circuit serves as an isolation circuit. The control signal .phi.2 falls (i.e. `L` level) during the period when the control signal .phi.1 is at the H level. Thus, the output potential of the separation section on the inverting output side is held at the non-inverting output potential of the address signal Ai while that on the non-inverting output is held at the inverting output potential of the address signal Ai.
The refresh address input circuit section N3 produces an address signal corresponding to a refresh address.
The self-latch circuit N4 latches the output potential of the isolation circuit section after the control signal .phi.2 has fallen and sends the latched potential to the driver circuit section.
The driver circuit section N5 converts the signal inputted in accordance with the address signal Ai. Thus, it outputs the inverted signal of the address signal Ai from the inverting output side and the non-inverted signal of the address signal Ai from the non-inverting output side. Additionally, a capacitor having a relatively large capacitance of 2-3 pF is connected with the output from the driver circuit for the DRAM. In comparing of the delay times due to the different load capacitances for a MOS transistor and a bipolar transistor, as seen from FIG. 3 as disclosed in the pending application U.S. Ser. No. 462,986 filed Jan. 10, 1990, if the load capacitance is relatively large, the BiCMOS circuit, the output stage of which is constructed by a bipolar transistor, provides a higher operation speed. For this reason, in most cases, the driver circuit section N5 DRAM is designed in a BiCMOS structure composed of, e.g., a CMOS inverter and a bipolar transistor Tr1 as shown in FIG. 2.
The above prior art has the following problems to be solved.
The delay time generated in the input buffer circuit is the sum of the time required for the gate insulating film of each of logic gates constituting it to be charged/discharged by an input signal and to charge/discharge the output load capacitance by an output signal. The delay time generated in the entire input buffer circuit, therefore, is substantially determined by the number of logic gates. Accordingly, by reducing the number of logic gates from the input section to the output section of the input buffer circuit, the operation speed can be improved.
On the inverting output side, the input buffer circuit of the above prior art has the following 5 (five) logic gates from its input section to output section:
the first stage: the level converter circuit section IC1: PA0 the second stage: the complementary signal creating circuit IC2: PA0 the third stage: the complementary signal creating circuit IC3a: PA0 the fourth stage: the isolation circuit unit IC4: PA0 the fifth stage: the driver circuit IC5. PA0 the first stage the level converter circuit section IC1: PA0 the second stage: the complementary signal creating section IC3b PA0 the third stage: the isolation circuit section IC4; and PA0 the fourth stage: the driver circuit section IC5
On the other hand, on the non-inverting output side, the inverter IC2 of the complementary signal creating circuit section is not required in contrast to the inverting output side, the input buffer circuit has only to have the following 4 (four) logic gates:
Now it should be noted that the delay time of the entire input buffer circuit is determined by the number of logic gates on the inverting output side having more logic gates so that the prior art input buffer circuit substantially has five logic gate stages. Therefore, if the input buffer circuit is designed to have the smaller number of logic gates than 5, an input buffer capable of operating at a higher speed than before can be realized.
Further, the above prior art, in which the inverting output side and the non-inverting output side have different numbers of logic gate stages, provides a difference in the delay time between complementary signals AN and AP. The presence of this difference in the delay times for the complementary signals, which are supplied to the decoder circuits, may generate a hazard in the decoder circuit, thereby badly influencing the circuit operation.
The difference in the number of logic gates can be obviated by inserting an non-inverting buffer of one stage of a logic gate on the non-inverting output side having a smaller number of logic gates without substantially increasing the number of logic gates in the input buffer circuit.
However, the operation speed of the non-inverting buffer circuit of one logic gate stage is slower than that of the inverting buffer circuit, as described below in detail. Therefore, coincidence in the number of logic gates does not lead to that in the delay time; on the contrary, the delay time will be increased.
Now, the problem attendant on the conventional non-inverting buffer will be explained in connection with the case where the driver circuit N5 is designed in the non-inverting buffer circuit in a BiCMOS structure in which a pMOS Q51 is connected between the base and the collector of a bipolar transistor Tr 51 as shown in FIG. 5.
In FIG. 5, when an input signal V.sub.IN shifts from the `H` level to the `L` level, Q51 also shifts from the off-state to on-state. Then, the base current is supplied to Tr51 so that Tr51 turns on and so the collector current IC flows. Thus, the collector potential (output potential V.sub.OUT) approaches the `L` level. However, when the collector potential approaches (VBE+Vth) (sum of the base-emitter voltage and the threshold potential of Q51), Q51 performs a sub-threshold operation to greatly reduce the capability of supplying the base current. As a result, as shown in FIG. 6, the gradient of the collector potential V.sub.OUT becomes moderate in the neighborhood of the `L` level. This increases the delay time and also generates the through-current in the logic gate of a MOS transistor connected with the succeeding stage thereby to increase current consumption.